This application claims priority from Korean Patent Application No. 2001-8758, filed Feb. 21, 2001, the contents of which are hereby incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates generally to a semiconductor device comprising a bonding pad and a method of fabricating the same. More particularly, the present invention relates to a bonding pad of a semiconductor device and a method of fabricating the same.
2. Description of Related Art
A bonding pad is a terminal that connects integrated circuit patterns formed on a semiconductor chip to an external device. A semiconductor packaging process includes wire bonding to connect the bonding pad to a lead or solder ball. The lead or solder ball provides an external connection terminal of a semiconductor package and is typically used to connect to an external device through a gold wire. The external connection terminals of the semiconductor package are mounted on a printed circuit board that utilizes the semiconductor package.
In most wire bonding methods, a ball bond is formed as a first bond on the bonding pad of a semiconductor chip. A stitch bond is formed as a second bond either on an inner lead of a lead frame or on a substrate having a printed circuit board formed thereon. However, a particular wire bonding process, known as beam lead bonding, is generally used in highly-integrated semiconductor packages, such as a chip scale package (CSP). A representative semiconductor package using this beam lead bonding technique is a Micro-Ball Grid Array (xcexc-BGA) package, such as one developed by Tessera, Inc.
In the beam lead bonding process, a bonding tool is used to compress a gold-plated copper beam lead onto the bonding pad. The compression bonding is typically thermo-compression bonding. Unfortunately, beam lead bonding asserts a greater mechanical force on the bonding pad than conventional wire bonding, and thereby causes increased mechanical stress in the bonding pad.
FIG. 1 is a cross-sectional view of a bonding pad illustrating a beam lead bond on a bonding pad of a conventional semiconductor device. FIG. 2 is a plan view of a metal open defect that occurs when a bond pull test (BPT) is performed on the beam lead bonded bonding pad.
Referring first to FIG. 1, a bonding pad 20 is formed on a semiconductor substrate 2. The bonding pad 20 typically includes a substructure 4 that carries out the same functions as a semiconductor memory. The substructure 4 is formed on a semiconductor substrate 2. A dielectric layer 6 is formed on the substructure 4 and a metal layer 8 is formed on the dielectric layer 6. Beam lead wire bonding is performed on the metal layer 8. After the beam lead bonding is performed, a temperature cycling test is performed for a predetermined time. A BPT is then performed to verify the reliability of the beam lead bonding.
The temperature cycling test is a reliability test to check for physical and electrical defects in a semiconductor device. In the temperature cycling test, the temperature of the semiconductor device is repeatedly raised and lowered between about xe2x88x9265xcx9c150xc2x0 C. in a closed chamber. The BPT is a reliability test used to check the amount of separation force required to separate the bonding wire from the bonding pad. The BPT is also used to analyze a separation portion of the beam lead 30 and to check the normal performance of a beam lead bonding. The BPT is performed by pulling the beam lead 30 up with a predetermined force to determine the adhesiveness between the beam lead 30 and the surface of the bonding pad 20.
As illustrated in FIG. 1, if the beam lead 30 is properly wire-bonded, the beam lead 30 detaches from the surface of the bonding pad 20 at points A and B. If the beam lead 30 wire bonding is defective, however, the beam lead 30 detaches from the surface of the bonding pad 20 at point C or a metal open failure occurs at point D and the metal layer 8 underneath the bonding pad 20 detaches. In other words, during the BPT, the beam lead 30 may detach at point C if it is not compressed properly to the surface of the bonding pad 20. The metal layer 8 detaches at point D if adhesion between the metal layer 8 and the dielectric layer 6 of the bonding pad 20 is weak, if the bonding pad 20 is mechanically stressed by the beam lead bonding to the point that delamination occurs between the dielectric layer 6 and the metal layer 8, or if the dielectric layer 6 is broken.
With reference to FIG. 2, on the left of FIG. 2, the beam lead 30 is shown bonded to the bonding pad 20 of the semiconductor substrate 10. On the right of FIG. 2, the metal layer 8 is shown detached from the bonding pad 20 due to a metal open defect occurring during a BPT. The metal open defect, generated in a xcexc-BGA package, caused by poor adhesiveness of the layers on a semiconductor substrate, causes the semiconductor substrate to be nonfunctional.
Unfortunately, during the BPT test, the beam lead 30 is often either too easily separated from the bonding pad 20, or a defect such as a metal open defect is generated when the stacked layers (substructure 4, the dielectric layer 6, and the metal layer 8) of the bonding pad 20 are poorly adhered to each other.
To solve the forgoing problems, the present invention provides a bonding pad of a semiconductor device that has improved wire bonding reliability in a semiconductor package where beam lead bonding is performed.
Also, the present invention provides a semiconductor package and a semiconductor package module on which a semiconductor chip having the bonding pad is mounted.
Additionally, the present invention provides a method of fabricating a bonding pad of a semiconductor device that can enhance the reliability of wire bonding in a semiconductor package where beam lead bonding is performed.
Accordingly, a preferred bonding pad of a semiconductor device includes a semiconductor substrate. A substructure is formed on the semiconductor substrate. A first dielectric layer is formed on the substructure. A polysilicon film plate is formed on the first dielectric layer to improve the physical characteristics of the wire bonding. A first metal layer is formed on the polysilicon film plate. A second metal layer formed on the first metal layer.
According to another aspect of this invention, a semiconductor package and a semiconductor package module on which a semiconductor chip having a bonding pad is mounted include a semiconductor substrate. A substructure is formed on the semiconductor substrate. A first dielectric is layer formed on the substructure. A polysilicon film plate is formed on the first dielectric layer to improve the physical characteristics of the bonding pad. A first metal layer is formed on the polysilicon film plate. A second metal layer is formed on the first metal layer.
Preferably, the substructure comprises circuitry that performs the functions of a memory device, such as a DRAM, and the wire bonding is beam lead bonding. The first dielectric layer is preferably a boron phosphor silicate glass (BPSG) layer. The first dielectric layer preferably has a thickness of around 3000-4000 xc3x85. The polysilicon film plate preferably has a thickness of about 1000-2000 xc3x85. The first and second metal layers are preferably formed of aluminum. The first metal layer preferably has a thickness of around 7000-7500 xc3x85 and the second metal layer has a thickness of about 8500-9000 xc3x85.
A method of fabricating a bonding pad of a semiconductor device is also provided. According to this method, a polysilicon film plate is formed on a semiconductor substrate to improve physical characteristics of the bonding pad during wire bonding. A second dielectric layer is also formed on the semiconductor substrate on which the polysilicon film plate is formed. An area is etched in which a bonding pad will be formed. A first metal layer is then formed to cover a portion of the second dielectric layer and to contact the polysilicon film plate. An inter-metal dielectric layer (IMD) is formed on the semiconductor substrate on which the first metal layer is formed and an area in which a bonding pad will be formed is etched. A second metal layer is formed to cover a portion of the inter-metal dielectric layer (IMD) and to contact the first metal layer. A passivation layer is formed on the semiconductor substrate on which the second metal layer is formed and the bonding pad area is etched. A first dielectric layer is formed on the substructure before the polysilicon film plate is formed. The polysilicon film plate preferably has a thickness of about 1000-2000 xc3x85. While forming the passivation layer, an oxide layer is preferably formed by high density plasma (HDP) deposition and a nitride layer is formed by PE chemical vapor deposition (PECVD) on the oxide layer.
According to various preferred embodiments of this invention, a polysilicon film plate is formed between a bonding pad metal layer, where a first metal layer contacts a second metal layer, and a first dielectric layer. Due to the presence of the polysilicon film plate, external thermo-mechanical stress is absorbed, and durability against stress in a vertical direction is increased. Also, the bonding of the bonding pad metal layer and the dielectric layer is improved.